CSIRAC design

Plaque detailing the loan of CSIRAC to the University of Melbourne.

CSIRAC was, of course, a vacuum-tube machine; most of its 2000 tubes were 6SN7, 6V6, EA50 and KT66. Eventually button-based tubes were used in the delay line store electronics, germanium diodes and, much later, George Semkiw re-designed the disk read electronics using germanium transistors.

The logical design of CSIRAC was directed toward achieving engineering and programming simplicity, even at the expense of speed of execution.

From the engineering point of view, simplicity was achieved by the use of strictly serial processing and adopting a relatively small word length of 20 bits (today’s computers use mostly 16, 32 or even 64 bit word lengths). Storage delay lines each held 16 such words serially, and at first no attempt was made to minimise the time lost waiting for a word coincidence to occur, as was done, for instance, in the EDSAC. Consequently, with 1-microsecond digits at 3-microsecond digit periods and a delay line of 960-microsecond “length", the initial basic execution rate was about 500 instructions per second, and all instructions, except multiplication, took the same amount of time. Later the instruction execution rate was raised to about 1000 instructions per second (today’s computers have an execution rate of upwards of 100,000,000 instructions per second), and the store capacity was doubled using a method, developed by Reginald Ryan, of interleaving two trains of digits in each physical delay line so that each line held 32 words of 20 bits.

The instruction set

The instruction partitioning, although somewhat more complex than that of a simple one-address system like the EDSAC or even TREAC, was certainly less complex than that of the ACE or EDVAC. These features of simplicity of instruction format and economy in program length, resulting from flexibility and economy of instructions needed to perform a complex function, made CSIRAC notable.

Instructions consisted of three components, a 5-bit “destination” P1-P5, a 5-bit “source" P6-P10, and a 10-bit “address" P11-P20. For instructions that used the main store, the 6 bits P15-P20 selected one of the 64 logical delay lines. Bits P11-P14 determined the time at which 20 bits of data were written to or extracted from the delay line, and thus represented address of a word within the selected delay line. There were 32 destination gates and 32 source gates; the 10 address bits identified a data word within the store if either the source or destination required access to the store. The advantage of having the store address in the P11-P20 group of a word was that of simplifying address variation under program control. The total number of source and destination combinations, or different instruction functions, was 1024, although only about 256 of these were used often. This functional flexibility and small number of instruction segments undoubtedly made the machine attractive to users.

The 20 bit word was adopted deliberately! Although this short length limited the precision of arithmetic, it was adequate for most of the engineering-type calculations that occupied much of CSIRAC’s time. It also allowed further engineering simplicity. This short length was an advantage to the programming objective: using the machine as a vehicle to develop programming techniques. For instance, it enforced development of double multiple-word-length and floating-point arithmetic routines, and of interpretive processes. These routines, however, had the disadvantages of slowing some computations and occupying valuable extra storage.